VHDL Programming

CPU: Synthesis Description 307

c

sel

ab

ALU

Figure 13-2
ALU Interface.

Inputs aand bare the two input busses upon which the ALU operations

are performed. Output bus creturns the result of the ALU operation. Input

seldetermines which operation is performed as specified by Figure 13-3.

As we can see, the ALU can perform a number of arithmetic operations,

such as add and subtract, and some logical operations, such as AND, OR,

and XOR. Following is a VHDL description of the ALU entity:

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

use work.cpu_lib.all;

entity alu is

port( a, b : in bit16;

port( sel : in t_alu;

port( c : out bit16);

end alu;

architecture rtl of alu is

begin

aluproc: process(a, b, sel)

begin

case sel is

when alupass =>

c <= a after 1 ns;

when andOp =>

c <= a and b after 1 ns;

when orOp =>

c <= a or b after 1 ns;

when xorOp =>

c <= a xor b after 1 ns;