VHDL Programming

CPU: Synthesis Description 309

Comp

The next component described is the comparator entity comp. This entity

compares two values and returns either a ‘ 1 ’or ‘ 0 ’depending on the

type of comparison requested and the values being compared. A symbol

showing the ports of the comparator is shown in Figure 13-4.

The comparison type is determined by the value on input port sel.For

instance, to compare if inputs aand bare equal, apply the value eqto port

sel. If ports aand bhave the same value, port compoutreturns ‘ 1 ’. If the

values are not equal,‘ 0 ’is returned. The types of comparisons allowed are

described by type t_compin package cpu_libin file cpulib.vhddescribed

earlier. The full table of comparison types and values is shown in Figure 13-5.

All operations work on two input values and return a single bit result.

This bit is used to control the flow of operation within the processor while

executing instructions. Following is a VHDL description of the compentity:

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

compout

sel

ab

Comp

Figure 13-4

Comp Interface.

Sel input value Comparison

EQ Compout = 1 when a equals b

NEQ Compout = 1 when a is not equal to b

GT Compout = 1 when a is greater than b

GTE Compout = 1 when a is greater than or equal to b

LT Compout = 1 when a is less than b

LTE Compout = 1 when a is less than or equal to b

Figure 13-5
Comp Operation
Table.