CPU: Synthesis Description 311
The comparator consists of a large casestatement where each branch
of the casestatement contains an IF. If the condition tested is true, a ‘ 1 ’
value is assigned; otherwise, a ‘ 0 ’is assigned. Again, each assignment
occurs after 1 nanosecond to remove delta delay problems.Control
The controlentity provides the necessary signal interactions to make the
data flow properly through the CPU and perform the expected functions.
Architecture rtlcontains a state machine that causes all appropriate signal
values to update based on the current state and input signals and produce
a next state for the state machine. A symbol for the control block is shown
in Figure 13-6.
The control symbol has only a few inputs, but a lot of outputs. The
control block provides all of the control signals to regulate data traffic for
the CPU. Following is the VHDL description for the CPU:library IEEE;
use IEEE.std_logic_1164.all;
use work.cpu_lib.all;entity control is
port( clock : in std_logic;
port( reset : in std_logic;
port( instrReg : in bit16;
port( compout : in std_logic;
port( ready : in std_logic;
port( progCntrWr : out std_logic;
port( progCntrRd : out std_logic;
port( addrRegWr : out std_logic;
port( addrRegRd : out std_logic;
port( outRegWr : out std_logic;
port( outRegRd : out std_logic;
port( shiftSel : out t_shift;
port( aluSel : out t_alu;
port( compSel : out t_comp;
port( opRegRd : out std_logic;
port( opRegWr : out std_logic;
port( instrWr : out std_logic;
port( regSel : out t_reg;
port( regRd : out std_logic;
port( regWr : out std_logic;
port( rw : out std_logic;
port( vma : out std_logic
port);
end control;