VHDL Programming

CPU: Synthesis Description 325

0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1

0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0

•••••••••

Shift Left

'0'

0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0

•••••••••

Shift Right

'0'

Figure 13-10
Shift Operations.

when rotl =>

y <= a(14 downto 0) & a(15) after 1 ns;

when rotr =>

y <= a(0) & a(15 downto 1) after 1 ns;

end case;

end process;

end rtl;

The shftpassmode allows the shifter to pass the input data to the

output without any shift operations. This mode is quite common because

all of the ALU operations flow through the shiftentity, and very few

instructions are actually performing a shift operation.