VHDL Programming

(C. Jardin) #1

328 Chapter Thirteen


q <= “XXXXXXXXXXXXXXXX” after 1 ns;
-- exemplar_translate_on
end if;
end process;
end rtl;

The functionality is described by two processes that use a signal to
communicate much like the regarrayentity. The first process controls
when signal valis written. Signal valis written only on the rising edge
of input clk. The second process transfers the value of signal valonly
when input enis a ‘ 1 ’value; otherwise, a value of ‘Z’is output.

SUMMARY


When all of these entities are connected together correctly, the function-
ality of the CPU results. The next two chapters focus on simulating the
design for proper operation and synthesizing the design to a target device.
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