CPU: RTL Simulation 337
early in the design process when no known good results exist to verify
against. When the results are verified, these results become the known
good results to verify future versions or minor changes to the design.Full Testbench
A full testbench is very similar to a stimulus only testbench except that the
full testbench also includes the capability to check the output of the DUT.
The full testbench applies the stimulus to the design and then examines the
outputs of the design to see if the output results of the DUT match known
good results.
Following is a full testbench for the counter:ENTITY testbench IS END;------------------------------------------------------------
-- FULL TESTBENCH
-- testbench for counter
-- reads from file “counter.txt”
------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE std.textio.ALL;
USE ieee.std_logic_textio.all;
USE WORK.count_types.all;
ARCHITECTURE full OF testbench IS-----------------------------------
-- component declaration for counter
-----------------------------------COMPONENT count
PORT (clk : IN std_logic;
ld : IN std_logic;
up_dwn : IN std_logic;
clk_en : IN std_logic;
din : IN bit8;
qout : INOUT bit8);
END COMPONENT;SIGNAL clk, ld, up_dwn, clk_en : std_logic;
SIGNAL qout, din : bit8;BEGIN
-- instantiate the component
uut: count
PORT MAP(clk => clk,
ld => ld,