VHDL Programming

(C. Jardin) #1

344 Chapter Fourteen


read(l, r, good => good_number);
NEXT WHEN NOT good_number;

vector_time := r * 1 ns; -- convert real
number to time
IF (now < vector_time) THEN -- wait until the
vector time
WAIT FOR vector_time - now;
END IF;

read(l, space); --- skip a space

-- read ld value
read(l,tmpld, good_val);
assert good_val REPORT “bad ld value”;

-- read up_dwn value
read(l,tmpup_dwn, good_val);
assert good_val REPORT “bad up_dwn value”;

-- read clk_en value
read(l,tmpclk_en, good_val);
assert good_val REPORT “bad clk_en value”;

read(l, space); --- skip a space

-- read din value
read(l, tmpdin, good_val);
assert good_val REPORT “bad din value”;

ld <= tmpld;
up_dwn <= tmpup_dwn;
clk_en <= tmpclk_en;
din <= tmpdin;

END LOOP;
ASSERT false REPORT “Test complete”;
WAIT;
END PROCESS;
END;

The hybrid testbench example looks very similar to the stimulus only
testbench example except that, right after the countercomponent instan-
tiation, the system clock is generated by a signal assignment statement.
Signal clkis assigned the value of not clkafter 10 nanoseconds. This
statement creates a periodic waveform with a period of 20 nanoseconds.
The testbench does not read signal clockfrom the vector file. The vector
file contains changes only on signals other than clock. This results in a
much smaller file that can be read much faster. Following is the hybrid
vector file:
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