VHDL Programming

CPU: RTL Simulation 347

(250 ns, ‘ 1 ’, ‘ 0 ’, ‘ 1 ’, 201, 160),

(260 ns, ‘ 0 ’, ‘ 0 ’, ‘ 1 ’, 0, 161));

VARIABLE ev_time : time;

BEGIN

FOR i in stim_array’RANGE LOOP

ev_time := stim_array(i).event_time;

IF (now < ev_time) THEN -- wait until the

vector time

WAIT FOR ev_time - now;

END IF;

-- assign ld value

ld <= stim_array(i).ld;

-- assign up_dwn value

up_dwn <= stim_array(i).up_dwn;

-- assign clk_en value

clk_en <= stim_array(i).clk_en;

-- assign din value

din <= stim_array(i).din;

-- check qout value

assert qout = stim_array(i).qout REPORT “vector

mismatch”;

END LOOP;

ASSERT false REPORT “Test complete”;

WAIT;

END PROCESS;

END;

The fast testbench looks similar to the other testbench styles in that it

has a top-level entity that instantiates a DUT and a process that generates

the stimulus. What’s different is that, instead of reading the stimulus

vectors from a file, the vectors are compiled into the testbench model.

The testbench declares a record type that contains a field for each

input signal (and output signal, if a full testbench is being modeled).

Next, the model declares an array of the record type that contains the

vector values. A variable of the array type is declared and then initialized

with the vector values. A whileloop reads each record of the array, waits

until the vector time is active, and applies the vector values to the design

inputs, similar to the way the file was read using TextIO. Notice that array

and record indexing is used to select each signal value.