CPU: RTL Simulation 351
Figure 14-5
Waveform Display of
the Reset Sequence.vcom regarray.vhd
vcom trireg.vhd
vcom cpu.vhd
vcom mem.vhd
vcom top.vhdAfter all of the files have been compiled, the design can be loaded into
the simulator for verification. This can be initiated from the GUI or from
the command line with the following command:vsim -lib work top behaveThis command specifies the library (work), entity (top), and architecture
(behave) or configuration to simulate. After the design has been loaded,
the simulator needs stimulus for the design and specification of what data
to monitor. For this simulation, the current_state, the memory interface,
program counter, and other signals are monitored. Figure 14-5 shows a
waveform display of the reset sequence of the CPU.
From this display, we can verify that the CPU is functioning properly.
At time 0, the resetsignal is set to a ‘ 1 ’value, which puts the CPU into
state reset1, the first state of the reset sequence. After the reset signal
is set to ‘ 0 ’, the CPU can begin performing the reset sequence. The two
most interesting signals to examine are current_stateand next_state.
Notice that, while the resetinput is a ‘ 1 ’, the CPU remains in state
reset1. After signal resetis set to a ‘ 0 ’, on the next rising edge of signal
clock,current_stateadvances to state reset2.
Each clock rising edge after that causes the CPU to advance to the next
state. At state reset3, the data bus receives the value 0000 to be used as
the starting address for the first instruction. At state reset4, register