CPU: RTL Simulation 353
Figure 14-7
A Waveform Display
Showing the Store
Instruction.
After the load instruction has executed all of the states, to complete the
load instruction, the CPU advances to a set of states that increments
the program counter register to point to the next instruction.
The CPU performs three load instructions to load the proper CPU
registers before the block copy can proceed. A final load instruction is
performed which loads the value to be copied into register 3. At this point,
the CPU program counter is pointing to address 7, a store instruction.
This instruction uses the address in reg 2 to store the value in reg 3 to
the new location. A waveform display showing the store instruction is
shown in Figure 14-7.
During state execute, the value of reg2is read to the data bus where it
is copied to the address register in state store2. During store3, register
array (3) drives the data bus with the data to be stored. During state
store4, the value is written to the memaddress.
After the store instruction is completed, the CPU checks to see if the
block copy operation has completed. This is accomplished by the instruction
at location 8, which branches back to instruction 00 if reg 1 is greater than
reg 6. This instruction execution is shown Figure 14-8.
The first step is to read the value of register 1. This value is stored to
register opregduring state bgti2. Next, the value of reg6is read and a
comparison is performed. Notice that signal compoutstays a ‘ 0 ’value
because the greater than operation failed; therefore, the branch operation
is be performed.
This set of instructions is performed a number of times until the
source array is copied to the destination array. The source array is shown
in Figure 14-9.
The array starts at location 16 and continues to location 31. The pattern
stored in the source array is a very simple one that starts at 1 and ends