CPU: RTL Simulation 355
Figure 14-10
The Destination Array
Before the Copy
Operation Has
Completed.
at 16. Figure 14-10 shows the destination array before the copy operation
has completed.
The destination array starts at location 48 and ends at location 63. The
destination array is shown after two copy operations have been performed.
Notice that location 48 has the first value, and location 49 has the second
value. A complete simulation run completely copies one array to another.
All of the examples that allow the reader to duplicate the simulation of
the CPU are found on the CD that comes with this book.SUMMARY
In this chapter, we examined what was necessary to perform a functional
verification of the CPU design and walked through one loop of the block
copy operation CPU simulation. In the next chapter, we synthesize the
CPU description to a target FPGA device for implementation.