VHDL Programming

The order that the files are read in is determined by the order in the

list. The first to be read is the top of the list. In VHDL the order of reading

files is important so that package files are read in before they are used.

Also the top level of the design should be read in last so that the design

is properly elaborated. In Figure 15-6 the list of files has been reordered

so that the package file,cpulib.vhd, is now read first, and the design top

level,cpu.vhd, is now read last. Files are moved in the list by selecting

them, and dragging and dropping to the new location. Now that the files

are in the proper order all the design files can be read into the synthesis

tool by selecting the Read button.

Now that the design has been read into the system, constraints can

be placed on the design to control how the design is implemented. For in-

stance timing constraints, input constraints, and output constraints can

all be entered at this point. For this example we will only enter a clock

constraint. The clock constraint will specify the minimum clock frequency

for the design. This will give the synthesis tool a target frequency with

which to implement all logic. The clock constraint is specified as shown

in Figure 15-7.

Now that the library has been loaded, the design files read in, and the

constraints specified, the design can be optimized. Select the Optimize tab

to invoke the optimization user interface. For this example optimizing for

area is used to create a small design. The hierarchy of the design will be

preserved to get an idea of the size of each block. In general if the design

CPU Design: Synthesis Results 361

Figure 15-5
Select Input Files.