VHDL Programming

Placing and Routing the Device

The target device for the CPU design, as mentioned in earlier chapters,

is an FPGA device. The device used is the Apex 20KE architecture from

Altera. The place and route tools used with the Apex 20KE architecture

are in the Quartus toolset. Quartus is a set of tools that includes not only

place and route, but VHDL entry, VHDL simulation, gate-level simulation,

and timing analysis. The first step in the process is to compile the design

into the place and route environment.

Setting up a project

Most tools that work on a design with multiple data descriptions have a

project manager to keep all of the files for that design in one place. This

facilitates file management of the design. The first step in the place and

route process is to set up a project. In the case of the Quartus environment,

the project is usually named the same as the output EDIF file from syn-

thesis. The Quartus user interface is shown in Figure 16-5.

Selecting the File Project Wizardmenu item will bring up a wizard

that walks the user through the creation of a new project. The first pane

Place and Route 373

Figure 16-5

Quartus User

Interface.