Chapter 17 CPU: VITAL Simulation

The last step in the high-density FPGA design process is

to run gate-level timing simulation of the design. Figure

17-1 shows the high-density FPGA design flow. The place

and route process produces a number of files that need to

be verified before the design is implemented. The gate-

level timing simulation process verifies that the design

from the place and route process is correct from a timing

and functional point of view.

Within VHDL, this process is implemented using VITAL.

VITAL is an IEEE standard that is used for modeling accu-

rate timing at the gate level. VITAL is an acronym for the

VHDL Initiative Toward ASIC Libraries. VITAL specifies a

standard method of writing ASIC or FPGA libraries so

that timing can be back-annotated. VITAL libraries used

in concert with a VITAL-compliant VHDL simulator can

perform gate-level timing simulation of the target design.

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