VHDL Programming

380 Chapter Seventeen

The VITAL process is shown in Figure 17-2.

The place and route tools generate two VITAL-compliant simulator

input files. The first is a VHDL netlist that contains the interconnections

of all of the entities used to model the design. The second is a timing-

accurate SDF back-annotation file used to input post-route timing into

the VITAL simulation. There is a third input needed to the simulation

process. The third input is the VITAL library that describes all of the

behavior of the entities used to implement the design. In the next few

sections, we examine each of these in more detail.

Design Specification

HDL Capture

RTL Simulation

RTL Synthesis

Functional

Gate Simulation

Place and Route

Post Layout Timing

Simulation

Figure 17-1
High-Density Design
Flow.