VHDL Programming

Behavioral Modeling 21

A

B

0 10 20 30 40

AB

Delay = 20 ns

Figure 2-4
Inertial Delay Buffer
Waveforms.

event at 30 nanoseconds did not have enough time to overcome the inertia

of the output signal.

The inertial delay model is by far the most commonly used in all cur-

rently available simulators. This is partly because, in most cases, the

inertial delay model is accurate enough for the designer’s needs. One

more reason for the widespread use of inertial delay is that it prevents

prolific propagation of spikes throughout the circuit. In most cases, this

is the behavior wanted by the designer.

Transport Delay

Transport delay is not the default in VHDL and must be specified. It repre-

sents a wire delay in which any pulse, no matter how small, is propagated

to the output signal delayed by the delay value specified. Transport delay

is especially useful for modeling delay line devices, wire delays on a PC

board, and path delays on an ASIC.

If we look at the same buffer circuit that was shown in Figure 2-4, but

replace the inertial delay waveforms with the transport delay waveforms,

we get the result shown in Figure 2-5. The same waveform is input to

signal A, but the output from signal B is quite different. With transport

delay, the spikes are not swallowed, but the events are ordered before