VHDL Programming

CPU:Vital Simulation 381

VITAL Library

One of the reasons VITAL was developed was because there were no

standard methods of describing timing behavior in VHDL. With no standard

method of describing timing, there was also no standard method of

describing timing back-annotation. VHDL was also inefficient at modeling

gate behavior when compared to gate-level simulators optimized for

gate-level performance.

For all these reasons, VITAL was created to allow near gate-level

simulation performance with timing accurate models. Some of the features

available with VITAL are as follows:

Accurate specification of delays—Delays can be specified pin to

pin, be dependent on state, or specified in relation to a particular

occurrence of a condition.

Tabular

Output

Waveforms

Vital

Simulator

Place and

Route

Vital

Library

VHDL

Netlist

SDF

File

Figure 17-2

VITAL Data Flow.