VHDL Programming

-- functionality results

VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) :=

VARIABLE Results : (others => ‘X’);

ALIAS Y_zd : STD_ULOGIC is Results(1);

-- output glitch detection variables

VARIABLE Y_GlitchData : VitalGlitchDataType;

begin

-------------------------

-- Functionality Section

-------------------------

Y_zd := (IN2_ipd) AND (IN1_ipd);

----------------------

-- Path Delay Section

----------------------

VitalPathDelay01 (

OutSignal => Y,

OutSignalName => “Y”,

OutTemp => Y_zd,

Paths => (0 => (IN1_ipd’last_event, tpd_IN1_Y,

Paths => (0 => (TRUE),

Paths => (1 => (IN2_ipd’last_event, tpd_IN2_Y,

Paths => (1 => (TRUE)),

GlitchData => Y_GlitchData,

Mode => DefGlitchMode,

XOn => DefGlitchXOn);

end process;

end AltVITAL;

configuration CFG_AND2_VITAL of AND2 is

for AltVITAL

end for;

end CFG_AND2_VITAL;

The model looks like standard VHDL with some different packages

included. In fact, the model is standard VHDL. The entity contains decla-

rations for the STD_1164packages for the signal logic types, but also con-

tains USEclauses for the VITAL timing package. The VITAL timing pack-

age is needed in the entity for AND2to provide the type declarations for

the entity generics.

The entitystatement contains four generics that are used to pass

delay information to the model. Each of the generics has a prefix that

represents the type of the delay. Generic tipd_in1is an input delay for

input in1. Generic tipd_in2is an input delay for input in2. Generic

CPU:Vital Simulation 385