tpd_in1_ymodels the pin-to-pin delay from input in1to output y. Generic
tidp_in2_ymodels the pin-to-pin delay from input in2to output y.
The timing information passed to these generics comes from the SDF
file generated by the place and route tool. Each of the delays passed to
the entity is instance specific.
Each of the generics has a type associated with it that represents how
many delay values can be held. In this example, the generic contains two
values. Delay tr01represents the delay value when the signal changes
from a ‘ 0 ’to ‘ 1 ’value. Delay tr10represents the delay when the signal
changes from a ‘ 1 ’to ‘ 0 ’value.
The entity also contains other generics that control functionality of the
VITAL model. This example contains a generic called TimingChecksOn
that controls whether or not the timing check functions in the VITAL
model are executed or not. Finally, the entity contains the input and
output ports for the model.VITAL Architecture
The architecture for the VITAL model contains four distinct code areas.
These are the wire delay section, the timing violation section, the function
description section, and the path delay section. Not all models contain all
of these sections. Some models are purely combinational and do not need
timing check sections.Wire Delay Section
The first section of the architecture is the wire delay section. The AND2
architecture starts with a number of library declarations; but notice that
the architecture also uses the VITAL primitives package. After the
architecture statement, the architecture declares two local signals,
in1_ipdand in2_ipd, and an attribute. The two signals are used to
delay the input signals to the entity. The delay values applied to the two
input signals represent the wiring delays to connect the physical gates
together. For instance, in Figure 17-4, gate U1 drives gates U2 and U3.
The wiring from gate U1 to gate U2 causes 8 nanoseconds of delay in
the path, but the wiring from U1 to U3 causes 10 nanoseconds of delay
in the path. With separate input delay values for each input, the wiring
delays can be modeled correctly.386 Chapter Seventeen