and route tools and contains accurate timing for the device. The SDF file
contains timing information for all of the generics in the VITAL library
that need data passed to them. Following is a sample SDF file:(DELAYFILE
(SDFVERSION “2.1”)
(DESIGN “cpu”)
(DATE “10/25/97 10:59:58”)
(VENDOR “Altera”)
(PROGRAM “MAX+plus II”)
(VERSION “Version 7.2 RC2 2/14/97”)
(DIVIDER .)
(VOLTAGE :5:) (PROCESS “typical”) (TEMPERATURE :25:)
(TIMESCALE 100ps)(CELL
(CELLTYPE “DFF”)
(INSTANCE DFF_457)
(DELAY
(ABSOLUTE
(IOPATH (posedge CLK) Q (32:32:32) (32:32:32)))
(ABSOLUTE
(IOPATH (negedge PRN) Q (36:36:36) (36:36:36)))
(ABSOLUTE
(IOPATH (negedge CLRN) Q (37:37:37) (37:37:37)))
)(TIMINGCHECK
(SETUP D (posedge CLK) (2:2:2))
(HOLD D (posedge CLK) (10:10:10))
))
)The SDF file starts with a header section that describes the name of
the design the file will back-annotate, the vendor that generated the file, the
environment used to generate the timing numbers, and so on. After the
header, the file consists of a number of cells. Each cell in the SDF file rep-
resents an instance in the VHDL netlist produced by the place and route
tools. Each cell contains the type of cell, the instance name in the netlist,
and timing information to be back-annotated to the design. The VITAL-
compliant simulator reads the SDF file and matches the generics in the
VHDL source with the delay constructs in the SDF file. For instance, an
IOPATHconstruct in the SDF file specifies the rising and falling delays from
and input to an output signal. The IOPATHconstruct is converted into
generic names and values to be applied to the VITAL simulation. The de-
signer of the VITAL model must ensure that the names used in the SDF
model and the names of the generics used in the VITAL model match so
that the generics can be properly matched with proper timing values.CPU:Vital Simulation 393