The last section is a timing check section that contains timing infor-
mation for the timing checks of the cell, if they exist. The timing check
section of the SDF file is read by the VITAL simulator and extracts timing
information to plug into generics of the VITAL model. The timing check
generics control the timing values that are used in the timing checks of the
VITAL model while simulation is progressing.
The cell description in the preceding example is for the DFFmodel that
we looked at earlier. There are delay values for CLKto Q,PRNto Q, and CLRN
to Q, and values for the setup and hold check.VITAL Simulation
To run the VITAL simulation, the designer first compiles the VITAL li-
brary into a simulator library. The device manufacturers supply VITAL
libraries for their devices. Next, the VITAL netlist is compiled to the
working library, and, finally, the SDF file is read in to back-annotate
the timing data into the design. After these steps have been completed,
the designer runs the VITAL simulation in the same manner as the RTL
simulation that we ran earlier.
The first step is to compile the VITAL library into a simulator library
so that it can be referenced. It is best if this library is compiled into the
location specified by the netlist from the place and route tool so that no
manual code modification is necessary. The following shows the first few
lines of the VITAL netlist generated by the MaxPlusII place and route
tool. The complete netlist is on the CD. Notice that the VITAL netlist
expects the VITAL component declarations, package VCOMPONENTS, to be
located in a library named alt_vtl:-- MAX+plus II Version 7.2 RC2 2/14/97
-- Sat Oct 25 10:59:34 1997--LIBRARY IEEE;
USE IEEE.std_logic_1164.all;LIBRARY alt_vtl;
USE alt_vtl.VCOMPONENTS.all;--ENTITY cpu IS
-- PORT (
-- addr : OUT std_logic_vector(15 downto 0);
-- data : INOUT std_logic_vector(15 downto 0);
-- clock : IN std_logic;394 Chapter Seventeen