VHDL Programming

Appendix B: VHDL Reference Tables 437

Table B-1

Statement or Clause Example(s)

Function Declaration FUNCTION function_name (parameter1 :

parameter1_type;

parameter2 :

parameter2_type)

RETURN return_type;

Function Body FUNCTION function_name (parameter1 :

parameter1_type;

parameter2 :

parameter2_type)

RETURN return_type IS

BEGIN

--do some stuff

END function_name;

Generate Statement generate_label : FOR gen_var IN start TO end

GENERATE label : component_name PORT

MAP (.........);

END GENERATE;

Generic Declaration GENERIC (generic1_name : generic1_type;

generic2_name : generic2_type);

Generic Map GENERIC MAP (generic1_name => value1,

value2);

Guarded Signal Assignment g1 : BLOCK (clk = ‘ 1 ’ AND clk’EVENT)

BEGIN

q <= GUARDED d AFTER 5 NS;

END BLOCK;

IF Statement IF x <= y THEN

--some statements

END IF;

IF z > w THEN

--some statements

ELSIF q < r THEN

--some more statements

END IF;

IF a = b THEN

--some statements

ELSIF c = d THEN

--some more statements

ELSE

--even more statements

END IF;

Incomplete Type TYPE type_name;