Behavioral Modeling 27
ENTITY reg IS
PORT( a, clock : in bit
PORT( d : out bit);
END reg;ARCHITECTURE test OF reg IS
SIGNAL b, c : bit;
BEGIN
b <= NOT(a); -- notice no delay
c <= NOT( clock AND b);
d <= c AND b;
END test;Drivers
VHDL has a unique way of handling multiply driven signals. Multiply
driven signals are very useful for modeling a data bus, a bidirectional bus,
and so on. Correctly modeling these kinds of circuits in VHDL requires
the concept of signal drivers. A VHDL driver is one contributor to the
overall value of a signal.
A multiply driven signal has many drivers. The values of all of the
drivers are resolved together to create a single value for the signal.
The method of resolving all of the contributors into a single value is
through a resolution function(resolution functions are discussed in Chapter
5, “Subprograms and Packages”). A resolution function is a designer-
written function that is called whenever a driver of a signal changes value.Driver Creation
Drivers are created by signal assignment statements. A concurrent signal
assignment inside of an architecture produces one driver for each sig-
nal assignment. Therefore, multiple signal assignments produce multiple
drivers for a signal. Consider the following architecture:ARCHITECTURE test OF test IS
BEGIN
a <= b AFTER 10 ns;
a <= c AFTER 10 ns;
END test;Signal ais being driven from two sources, band c. Each concurrent