VHDL Programming

Not only can objects be aliased in VHDL93 but functions can as well.

To specify a function aliasrequires a subprogram signature specification.

The signature specifies the types of the input parameters as well as the

type of the return parameter. An example is shown here:

ALIAS sub IS “-” [STD_LOGIC_VECTOR, STD_LOGIC_VECTOR,

RETURN STD_LOGIC_VECTOR];

This statement creates an aliascalled subfor an overloaded operator

function call that has two std_logic_vector input arguments and

returns a std_logic_vector.

Attribute Changes

There have been a number of new attributes added to VHDL93. They

reflect added functionality that was either difficult in VHDL87 or not pos-

sible. The following attributes have been added to VHDL93:

`ASCENDING

`DRIVING_VALUE

`IMAGE

`VALUE

`PATHNAME

`INSTANCE_NAME

`SIMPLE_NAME

`ASCENDING In VHDL87 it was tedious to find if a particular range

was ascending or descending. The `highand `lowattributes of the type

had to be compared to determine if the range was truly ascending, a null

range, or a single value. Attribute `ascendingwill return true if the range

is ascending or false if not. An example is shown here:

SUBTYPE descend IS STD_LOGIC_VECTOR( 7 DOWNTO 0);

SUBTYPE ascend IS STD_LOGIC_VECTOR(0 TO 7);

descend`ASCENDING --> false

ascend`ASCENDING --> true

`DRIVING_VALUE In VHDL87 the value of an output port could not

be read. To do this required the port mode of the port to be inout, or the

use of an internal signal. These workarounds caused an increase in

complexity that typically was not warranted and therefore to get around

this inconvenience VHDL93 adds attribute `driving_value. Attribute

`driving_valueallows the ability to read the value component of

450 Appendix D: VHDL93 Updates