BEGIN
-- ..
-- ..
d1 : dff PORT MAP( z, clock, qout);END ARCHITECTURE struct;CONFIGURATION topcon OF top IS
FOR struct
FOR d1 : dff GENERIC MAP( clk_to_q => 8.1 NS) PORT
MAP( q => dout );
END FOR;
END FOR;
END CONFIGURATION topcon;In this example, a dffcomponent is instantiated in entity top.A
configuration specification in the architecture declaration section spec-
ifies a value for the clk_to_qgeneric of 5.2 NS, and maps ports dand
clk. Port qis not mapped but is left open. After the end of the architec-
ture a configuration declaration specifies a new value for the clk_to_q
generic of 8.1 NS, and maps port qto dout. The new clk_to_qgeneric
value will override the previous value specified in the configuration spec-
ification.The mapping of port qmapped to open in the configuration
specification is also overriden with the new value doutas specified
in the configuration declaration.Postponed Process
In VHDL93 a new type of process has been added, the postponed
process.A postponed processis executed after all of the delta cycles
have been processed so that each signal receives the final value of a sim-
ulation time. A typical use for such a process is to perform timing checks.
There are cases in performing timing checks where the input signals need
to stabilize before the timing checks are performed. The postoned
processwill allow all of the input signals to stabilize, and finally the
postponed processwill be executed.
A postponed processis specified.p1: POSTPONED PROCESS( clk, reset) IS
-- postponed process declaration section
BEGIN
IF reset = ‘ 1 ’ THEN
--
END IF;
END PROCESS p1;Appendix D: VHDL93 Updates 459