VHDL Programming

the inertial delayspecified. In some cases this is too pessimistic. In

VHDL93 the modeler has the ability to specify a pulse rejectlimit which

can be less than or equal to the inertial delaythrough the device.

s1 <= REJECT 5 NS INERTIAL newval AFTER 15 NS;

In this example the inertial delaythrough the device is 15 NS, but the

reject limit is 5 NS. Any pulses of 5 NSor less will be rejected but pulses

greater than 5 NSwill be passed through with a 15 NSdelay.

Report Statement

In VHDL87 the reportclause could only be used within the assertstate-

ment, in VHDL93 a reportclause can exist separately. In VHDL87 if a

modeler wanted to issue a message to inform the designer that a partic-

ular piece of a model was executing, the following statement would have

been required:

ASSERT FALSE REPORT “entered file procedure read”;

The reportstatement would have to be called from an assertstate-

ment, and the assertcondition would need to return a false to trigger the

assertstatement. In VHDL93 the reportstatement can exist separately

so the following would also work:

REPORT “entered file procedure read”;

A reportstatement still has the ability to specify the severity level of

the message. In the above cases the severity level defaulted to error. If

some other severity was wanted, it could be specified as follows:

REPORT “entered timing check code” SEVERITY NOTE;

The severity clause at the end of the REPORTstatement allows the mod-

eler to specify any legal level of severity.

Shared Variables

A shared variable is one that is accessible by any design unit that includes

the package where the variable is declared. In VHDL87 variables could

Appendix D: VHDL93 Updates 461