only be declared in processes and were therefore local to the process. In
VHDL93 variables are now able to be declared in packages, and therefore
become global. Any design unit that includes the package can access the
variable. In the example here PACKAGE share has shared variable
timing_checks_ondeclared in it.PACKAGE share IS
VARIABLE timing_checks_on : BOOLEAN := TRUE;
END PACKAGE share;USE WORK.share.ALL;
ENTITY dff IS
PORT( din : IN STD_LOGIC;
clk : IN STD_LOGIC;
q : OUT STD_LOGIC);
END ENTITY dff;ARCHITECTURE behave OF dff IS
BEGIN
PROCESS(clk) IS
BEGIN
IF timing_checks_on THEN
-- timing check statements
END IF;
-- other statements
END PROCESS;
END ARCHITECTURE behave;USE WORK.share.ALL;
ENTITY jkff IS
PORT( j, k, clk, se, clr : IN STD_LOGIC;
q, qb : OUT STD_LOGIC);
END jkff;ARCHITECTURE behave OF jkff IS
BEGIN
PROCESS(clk, set, clr) IS
IF timing_checks_on THEN
-- timing check statements
END IF;
END PROCESS;
END ARCHITECTURE behave;PACKAGE shareis included by entities dffand jkff, making the variable
timing_checks_onglobally accessible by both entities. Global vari-
ables are very useful for passing information which is not really part of
the design functionality, but affect the simulation or synthesis operation.
In this example global variable timing_checks_onallows the ability to
turn off and on timing check operation. This does not affect the actual
functionality of the behavior of the models except to disable timing check
reporting. Another use for global variables is to use them to pass input
and output file handles.462 Appendix D: VHDL93 Updates