ARCHITECTURE behave OF test IS
BEGIN
---
END ARCHITECTURE behave;PACKAGE mypack IS
---
END PACKAGE mypack;PACKAGE BODY mypack IS
---
END PACKAGE BODY mypack;CONFIGURATION chip OF processor IS
---
END CONFIGURATION chip;COMPONENT memory IS -- notice addition of IS at end of
component clause
--
END COMPONENT memory;block1 : BLOCK IS
BEGIN
--
END BLOCK block1;proc1: PROCESS(clk, din) IS -- notice addition of IS at end
of process clause
BEGIN
--
END PROCESS proc1;RECORD myrec IS
--
END RECORD myrec;CASE selector IS
--
END CASE selector;lab: IF expr THEN
--
END IF lab;PROCEDURE convertval(...) IS
BEGIN
--
END PROCEDURE convertval;g1: FOR k IN 0 TO 7 GENERATE
BEGIN
--
END GENERATE g1;loop1: FOR k IN 0 TO 7 LOOP
--
END LOOP loop1;Appendix D: VHDL93 Updates 465