Index
469
a'HIGH(n), 154– 156
a'LEFT(n), 154– 156
a'LENGTH, 441
a'LOW(n), 154– 156
a'RANGE(n), 170– 171
a'REVERSE_RANGE(n), 170– 171
a'RIGHT(n), 154– 156
Access types, 96– 102
'ACTIVE, 160
Actuals, 183
Address register, 321– 322
Aggregate clause, 435
alias, 449– 450
Aliases, 215
ALU, 306– 308
ALU instructions, 292
AND gate symbol, 17
Apex 20KE architecture, 373
Architecture, 4– 5
Architecture configurations, 201– 203
Architecture local signals, 76
Architecture selection, 11
Arithmetic-logic unit (ALU),
306 – 308
Array types, 87– 93
Arrival time, 240– 241
'ASCENDING, 450
ASSERT statement, 56– 59
Asynchronous reset, 259– 260
At-Speed debugging, 399– 412
breakpoints, 406– 408
complex triggers, 410, 412
debug CPU design, 401– 404
debugger, 400, 401
implement new design, 405
instrument signals, 404
instruments, 401
trigger position, 408
watchpoints, 409– 410
waveform display, 408– 409
write instrumented design, 405
Attribute declaration, 435
Attribute specification, 435
Attributes
foreign interface, 455– 456
predefined, 143–171 (see also
Predefined attributes)
quick reference, 440– 442
synthesis, 239– 241
updates, 450– 452
user-defined, 218– 220Bachus-Naur format (BNF), 47,
445 – 447
Back-annotated simulation, 397– 398
'BASE, 169– 170
Based integer literal, 443
Based real literal, 443
Basic VHDL building blocks, 2– 3
'BEHAVIOR, 149– 151
Bit string literal, 443, 452
Block configurations, 199– 201
Block diagram of computer, 129
Block statements, 31– 37
Blocks, 31, 34
BNF, 47, 445– 447
Board-socket-chip analogy, 195– 199
Boolean optimization, 244
Branch instructions, 291
Breakpoints, 406– 408
Bridges2Silicon debugger, 400, 401
Buffer symbol, 20
Bus, 3CASE statement, 48–50, 256– 257
Changes to VHDL (seeVHDL93
updates)
Character literals, 81, 82, 443
clear, 261– 262
Clock constraints, 238– 239
Comparator, 256, 309– 311
Compile VHDL source dialog box, 350
Complex triggers, 410, 412
Component configurations, 176– 183
Component declaration, 436
Component instantiation, 436