VHDL Programming

(^476) Index
VHDL93 updates (Cont.):
REPORT statement, 461
rotate operators, 464
shared variables, 461– 462
shift operators, 463
syntax consistency, 464– 465
UNAFFECTED, 466
XNOR operator, 466– 467
VITAL, 379, 381– 382
VITAL AND gate, 383
VITAL architecture, 386
VITAL data flow, 381
VITAL descriptions, 382
VITAL level 0, 383
VITAL level 1, 383
VITAL library, 381– 382
VITAL packages, 382– 383
VITAL Primitives Package, 383
VITAL process, 380, 381
VITAL simulation, 379– 398
back-annotated simulation, 397– 398
flip-flop example, 388– 392
high-density design flow, 380
overview, 382
running the simulation, 394– 397
SDF file, 392– 394
simple VITAL model, 383– 386
wire delay section, 386– 388
VITAL Timing Package, 382– 383
vlib, 349
Voicemail controller, 266– 271
vsim, 351, 397
WAIT statements, 59– 66
multiple WAIT conditions, 63
sensitivity list, contrasted, 66
time-out clause, 64– 66
WAIT FOR, 62– 63
WAIT ON, 62
WAIT UNTIL, 62
WAIT FOR, 62– 63
WAIT ON, 62
WAIT time-out, 64– 66
WAIT UNTIL, 62
Warning, 56
Watchpoint expression, 409
Watchpoint Expression dialog box,
409, 411
Watchpoints, 409– 410
Waveform display, 408– 409
WHEN condition, 56
WHILE condition, 51
Wire delay, 242, 243
Wire delay section, 386– 388
XNOR operator, 466– 467