VHDL Programming

Behavioral Modeling 31

to out1. In the same way, component U2is mapped to signals inc, ind,

and out2.

Generic riseof instance U1is mapped to 10 nanoseconds, generic

fallis mapped to 12 nanoseconds, and generic loadis mapped to 3. The

generics for component U2are mapped to values 9 and 11 nanoseconds

and value 5.

Generics can also have default values that are overridden if actual

values are mapped to the generics. The next example shows two instances

of component type AND2.

In instance U1, actual values are mapped to the generics, and these

values are used in the simulation. In instance U2, no values are mapped

to the instance, and the default values are used to control the behavior of

the simulation if specified; otherwise an error occurs:

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

ENTITY test IS

GENERIC(rise, fall : TIME;

GENERIC(load : INTEGER);

PORT ( ina, inb, inc, ind : IN std_logic;

PORT ( out1, out2 : OUT std_logic);

END test;

ARCHITECTURE test_arch OF test IS

COMPONENT and2

GENERIC(rise, fall : TIME := 10 NS;

GENERIC(load : INTEGER := 0);

PORT ( a, b : IN std_logic;

PORT ( c : OUT std_logic);

END COMPONENT;

BEGIN

U1: and2 GENERIC MAP(10 ns, 12 ns, 3 )

PORT MAP (ina, inb, out1 );

U2: and2 PORT MAP (inc, ind, out2 );

END test_arch;

As we have seen, generics have many uses. The uses of generics are

limited only by the creativity of the model writer.

Block Statements

Blocks are a partitioning mechanism within VHDL that allow the designer