VHDL Programming

Behavioral Modeling 37

new signal is implicitly declared in the block whenever a block has a guard

expression. This signal is calledGUARD. Its value is the value of the guard

expression. This signal can be used to trigger other processes to occur.

Blocks are useful for partitioning the design into smaller, more man-

ageable units. They allow the designer the flexibility to create large

designs from smaller building blocks and provide a convenient method of

controlling the drivers on a signal.

SUMMARY

In the first chapter, concepts of structurally building models were discussed.

This chapter is the first of many that discusses behavioral modeling. In this

chapter, we discussed:

How signal assignments are the most basic form of behavioral

modeling

Signal assignment statements can be selected or conditional

Signal assignment statements can contain delays

VHDL contains inertial delay and transport delay

Simulation delta time points are used to order events in time

Drivers on a signal are created by signal assignment statements

Generics are used to pass data to entities

Block statements allow grouping within an entity

Guarded block statements allow the capability of turning off

drivers within a block