VHDL Programming

(C. Jardin) #1

66 Chapter Three


REPORT “sendA timed out at ‘ 1 ’”
SEVERITY ERROR;

sendB <= ‘ 1 ’ AFTER 10 ns;

end PROCESS B;
END wait_timeout;

Each of the WAITstatements now has a time-out expression specified as
1 usec. However, if the time out does happen, the ASSERTstatement reports
an error that the WAITstatement in question has timed out.

Sensitivity List Versus WAIT Statement


A process with a sensitivity list is an implicit WAIT ONthe signals in the
sensitivity list. This is shown by the following example:

PROCESS (clk)
VARIABLE last_clk : std_logic := ‘X’;
BEGIN
IF (clk /= last_clk ) AND (clk = ‘ 1 ’) THEN
q <= din AFTER 25 ns;
END IF;

last_clk := clk;

END PROCESS;

This example can be rewritten using a WAITstatement:

PROCESS

VARIABLE last_clk : std_logic := ‘X’;
BEGIN
IF (clk /= last_clk ) AND (clk = ‘ 1 ’) THEN
q <= din AFTER 25 ns;
END IF;

last_clk := clk;

WAIT ON clk;
END PROCESS;

The WAITstatement at the end of the process is equivalent to the sensi-
tivity list at the beginning of the process. But why is the WAITstatement
at the end of the process and not at the beginning? During initialization
of the simulator, all processes are executed once. To mimic the behavior
of the sensitivity list, the WAITstatement must be at the end of the process
to allow the PROCESSstatement to execute once.
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