VHDL Programming

(C. Jardin) #1

70 Chapter Three


Passive Processes


Passive processes are processes that exist in the entity statement part of an
entity. They are different from a normal process in that no signal assign-
ment is allowed. These processes are used to do all sorts of checking
functions. For instance, one good use of a passive process is to check the
data setup time on a flip-flop.
The advantage of the passive process over the example discussed in the
ASSERTstatement section is that, because the passive process exists in
the entity, it can be applied to any architecture of the entity. Take a look
at the following example:

LIBRARY IEEE;

USE IEEE.std_logic_1164ALL;
ENTITY dff IS
PORT( CLK, din : IN std_logic;
PORT( Q, QB : OUT std_logic);
BEGIN
PROCESS(CLK, din)
VARIABLE last_d_change : TIME := 0 ns;
VARIABLE last_clk, last_d_value : std_logic := ‘X’;
BEGIN
IF (din /= last_d_value) THEN
last_d_change := now;
last_d_value := din;
END IF;

IF (CLK /= last_clk) THEN
IF (CLK = ‘ 1 ’) THEN
ASSERT(now - last_d_change >= 15 ns)
REPORT “setup error”
SEVERITY ERROR;
END IF;

last_clk := CLK;
END IF;
END PROCESS;
END dff;

ARCHITECTURE behave OF dff IS
BEGIN
.
.
.
.
END behave;

ARCHITECTURE struct OF dff IS
BEGIN
.
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