VHDL Programming

74 Chapter Four

Object Types

A VHDL object consists of one of the following:

Signal, which represents interconnection wires that connect com-

ponent instantiation ports together.

Variable, which is used for local storage of temporary data, visible

only inside a process.

Constant, which names specific values.

Signal

Signal objects are used to connect entities together to form models. Signals

are the means for communication of dynamic data between entities. A

signal declaration looks like this:

SIGNAL signal_name : signal_type [:= initial_value];

The keyword SIGNALis followed by one or more signal names. Each

signal name creates a new signal. Separating the signal names from the

signal type is a colon. The signal type specifies the data type of the infor-

mation that the signal contains. Finally, the signal can contain an initial

value specifier so that the signal value may be initialized.

Signals can be declared in entity declaration sections, architecture

declarations, and package declarations. Signals in package declarations

are also referred to as global signals because they can be shared among

entities.

Following is an example of signal declarations:

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

PACKAGE sigdecl IS

TYPE bus_type IS ARRAY(0 to 7) OF std_logic;

SIGNAL vcc : std_logic := ‘ 1 ’;

SIGNAL ground : std_logic := ‘ 0 ’;

FUNCTION magic_function( a : IN bus_type) RETURN

bus_type;

END sigdecl;

USE WORK.sigdecl.ALL;

LIBRARY IEEE;