78 Chapter Four
and all of the instances of the constant value are updated to reflect the
new value of the constant.
A constant also provides a better-documented model by providing more
meaning to the value being described. For instance, instead of using the
value 3.1414 directly in the model, the designer should create a constant
as in the following:CONSTANT PI: REAL := 3.1414;
Even though the value is not going to change, the model becomes more
readable.
A constant declaration looks like this:CONSTANT constant_name {,constant_name} : type_name[:=
value];The valuespecification is optional, because VHDL also supports deferred
constants. These are constants declared in a package declaration whose
value is specified in a package body.
A constant has the same scoping rules as signals. A constant declared
in a package can be global if the package is used by a number of entities. A
constant in an entity declaration section can be referenced by any archi-
tecture of that entity. A constant in an architecture can be used by any
statement inside the architecture, including a process statement. A constant
declared in a process declaration can be used only in a process.Data Types
All of the objects we have been discussing until now—the signal, the
variable, and the constant—can be declared using a type specification to
specify the characteristics of the object. VHDL contains a wide range of
types that can be used to create simple or complex objects.
To define a new type, you must create a type declaration. A type dec-
laration defines the name of the type and the range of the type. Type
declarations are allowed in package declaration sections, entity declara-
tion sections, architecture declaration sections, subprogram declaration
sections, and process declaration sections.
A type declaration looks like this:TYPE type_name IS type_mark;