Gracemont cores are faster in many ways
than the original Skylake cores from 2015.
As an example, Intel compared Gracemont
against Skylake using SPECrate2017_
int_base. It provided 40 percent higher
performance using the same amount of
power, or the same performance with 40
percent less power. Even better, using a
multi-threaded test and comparing a 4-core
Gracemont configuration against a 2-core/4-
thread Skylake chip, Gracemont provided
80 percent more performance at the same
power, or used 80 percent less power at the
same ISO performance. Hyper-Threading
only provides about a 20 percent uplift in
performance compared to adding a physical
core, but the data is still promising as far as
power efficiency goes.
The problem is that Intel and other
processor companies like to play games with
statements about power and efficiency. Intel
locked the clocks on Gracemont cores to the
sweet spot in terms of efficiency to maximize
those numbers. In the real world, we’ve done
testing that suggests eight E-cores runningat up to 3.9GHz ends up delivering a similar
experience to an older Core i5-9400 (6-core, no
Hyper-Threading, running at up to 4.1GHz).
The E-cores often lead in general application
performance, but trail in gaming capabilities.
The kicker? Power consumption on the
12900K running only the E-cores ended up
being slightly higher than the i5-9400. But
there were still die space savings.
In terms of trimming the fat, Gracemont
features a clustered design with dual 3-wide
instruction decoders. This apparently allows
for a similar level of efficiency when compared
with a narrower 3-wide design, but it still
allows for decoding up to six instructions
per cycle. Intel also focused on improving the
branch efficiency (relative to the previous
Tremont architecture) via a 5,000-entry
branch target cache.
Where things get a bit wild is when we start
looking at the execution ports. Gracemont
features a 5-wide instruction allocation and
8-wide retire design, but it has 17 different
execution ports. Each of these ports tends
to be simplified relative to the Golden Cove
equivalents, and Intel says the arrangement
delivers higher integer IPC than Skylake at a
fraction of the power cost. The execution ports
consist of four integer ALUs, two load and
two store AGUs (address generation units),
two jump ports two integer store data ports,
two floating-point/vector store data ports,
and finally two FP/vector stacks with a third
vector ALU.
In terms of cache, each core gets a 64KB
instruction cache and a 32KB data cache—
that’s a 33 percent smaller data cache than
Golden Cove. Instead of individual L2 caches,
however, a cluster of four Gracemont cores
can share a 2MB L2 cache (4MB on data center
variants).
Gracemont cores are designed to run at
lower voltages, and since power scales with
the square of voltage, that helps a lot with
making them more efficient. Because of that
design parameter, Gracemont cores also won’t
clock nearly as high as Golden Cove. Where
the maximum turbo clocks on Golden Cove
cores can reach 5.2GHz, Gracemont cores peak
at a relatively tame 3.9GHz. That’s lower than
the Skylake 6700K’s 4.2GHz max boost clock,
six years later, all in the name of efficiency.
One interesting point here is that die shots
of Alder Lake indicate that Intel can cram
four Gracemont cores into approximately the
same area as a single Golden Cove core. The
Core i9-12900K has eight Golden Cove and
eight Gracemont cores, but a hypothetical
Gracemont-only design could have put 40
Gracemont cores into the same die area.
We are likely to see designs in the future
that omit all Golden Cove cores and simply
use a whole bunch of Gracemont cores, but
those will probably be for servers rather than
desktop users.Alder Lake needs
more complex and
intelligent thread
scheduling to maximize
performance—Windows
11, in other words.The Gracemont
architecture overview
looks more complex
than Golden Cove, but
despite having more
ports, it’s much smaller
and more efficient.the empire strikes back
32 MAXIMU MPC FEB 2022
© INTEL