Note that depending on if S changed first (case 1) or R changed the first (Case 2), final state
will be different, which means we have a critical race. To insure proper operation of well-designed asynchronous sequential logic circuits (no critical
race), allow only one external input signal to change at a time. This mode of operation is referred
to as “fundamental operating mode”. Transient, Meta-Stable State or Unstable Equilibrium State Output
This is another failure mode of latch circuits which causes the output to oscillate between 1 and 0 and
the final state may be unpredictable.
The cause may be:
Runt pulses
If two inputs feeding a gate are changed nearly simultaneously, a runt pulse may be
produced at the output of the gate.
Positive runt pulse
A positive-going pulse that begins with a value of 0 but doesn’t achieve the value of 1
Negative runt pulse
A negative-going pulse that begins with a value of 1 but doesn’t achieve the value of 0