Microsoft Word - Digital Logic Design v_4_6a

• If condition is true, T or “1” path is taken


• If condition is false, F or ”0” path is taken

 Oval shape is used for start, end and output box

 Example - Below is an ASM Chart example for a SR flip-flop derived from the state diagram:

• State exit conditions are the decision conditions in ASM.


• Emphasis is on state changes. All conditions that do not change the stay are not shown
  on the ASM chart.

 Timing Diagram
Another tool for describing the functionality of a sequential logic circuit is the timing diagram.
Although the timing diagram is not as scalable as State diagrams or ASM chart, it provides the timing
relationship between input and out signals.

 Basic definitions used in timing diagrams

 Timing Events

External input changes that cause changes in the output of a sequential logic circuit are

called timing events.

 Rise Time (tPLH)

The time it takes for a signal to go from a 10% to 90% value (an ideal timing diagram

assumes 0 seconds)

 Fall Time (tPHL)

The time it takes for a signal to go from a 90% to 10% value (an ideal timing diagram

assumes 0 seconds)

 Pulse Width

The time it takes for a signal to go from a 50% value on the rising edge to 50% value on the

falling edge.

 Average Propagation delay

In order to simplify a timing diagram, gate delays may be represented by an average

propagation delay tp where tp =( tPHL + tPLH)/2

(an ideal timing diagram assumes 0 seconds)

Q=0

Q=1

S.R

R

True False

False

The advantage of ASM is that it has two outputs

from each decision so it is clear if both conditions

are addressed and therefore the state machine is

completely specified.

True