Microsoft Word - Digital Logic Design v_4_6a

 An ideal timing diagram for an SR flip-flop
SR flip-flop discussed so far is an asynchronous sequential logic circuit since this latch circuit does
not rely on a system clock for synchronization.

Note: This is an ideal timing diagram where propagation delays are not shown.

 Design of Asynchronous Sequential Logic Circuit
Asynchronous Circuit does not rely on a clock which means that hazards may be a design problem.

 A couple of rules to avoid logic hazards and critical races:

 Rule 1 – One external input signal change at a time (fundamental mode)

 Rule 2 – Before the next external signal is allowed to change, the circuit must be given time

to reach a new stable state. (The circuit path with the longest delay dictates the speed of the

circuit.)

Q

R

S

Timing event

State time

(time between events)

1 2 3

90%

50%

10%

Pulse Width

tPLH tPHL^