Microsoft Word - Digital Logic Design v_4_6a

 Applying the Design Steps to an SR flip-flop

Note: This circuit encounters a critical race condition when SR transitions from 11 to 00.

 Designing a Clock Circuit (another simple asynchronous sequential logic circuit)

Start with state diagram

 Flow the design process

 Timing Diagram

You can increase the period T by one of the following methods:

• Adding to ∆t (more buffer)


• Adding more NOT gates (must be an odd number of gates)


• Adding an RC circuit and adjusting the time constant

Timing Event 1 2 3 4 5

Clock (CLK)

Propagation Delay, tp = Not Gate delay + ∆t

Period T = 2tp

Frequency f = 1/T=1/(2tp)

Duty Cycle DC = tp/T = tp /(2tp) = ½ = 50%

T

tp

Q+ = Q

Step 1. Write the

Compressed

Characteristic Table

Step 2. Draw

Compress K-map

Step 3. Draw the schematic

(since Q is used for Q+, we need a delay element)

Q^ ∆t

(delay)

Q+ Q=CLK

Q=0 Q=1

S R Q+

0 0 Q

0 1 0

1 0 1

1 1 0

Step 1. Write the

compressed

characteristic table

Step 2. Draw the

compressed K-map

Step 3. Draw the schematic

(since Q is used for Q+, we need a delay element)

Q 0 0 1

SR

00 01 11 10

Q S R

Q QR SR

= + +

+= +

( )

..

Apply DeMorgan’s

Theorem twice.

∆t

(delay)

Q+

R

S

Q

Q

Since Q and Q are provided, it is call a “double-rail

output”. If Q was the only output, then it would be

called a single-rail output.