Microsoft Word - Digital Logic Design v_4_6a

 Mixed-type Synchronous Finite State Machine

Some outputs are Mealy-type and others are Moore-type.

 Analyzing Synchronous Systems (General)

There are five steps in analysis of this type of circuit:

1) Assign a present state variable to each flip flop in the synchronous system.

Yi represents flip-flop outputs for i = 1, 2, 3, ...

2) Write the excitation-input equation for each of the flip-flops and the external-output

(Moore and/or mealy equations). After completing this step, Di, Ji Ki, Ti should be

defined where i=1, 2, 3 ... {# of flip-flops used}.

3) Substitute the excitation input equation into the characteristic equations of the flip-

flops to obtain the “next state” equations.

For D flip-flops  Yi+ = Di for i=1, 2, 3, ...

For J-K flip-flops  Yi

+

= Ji.Yi’ + Ki’.Yi for i=1, 2, 3, ...

For T flip-flops  Yi+ = Ti <XOR> Yi for i=1, 2, 3, ...

4) Obtain a PS/NS table or a composite K-map using the next state and external-out

(Mealy and/or Moore) equations. Separate K-maps can be used for the external

Excitation

Forming Logic

(Combinational)

Flip Flops

Input

Output

System Clock

Clock

External
Inputs (Xs)

Mealy

External Output

Ys Zs(Ys, Xs)

Excitation

input

Feedback

Mealy Output

Forming Logic

(Combinational)

Moore Output

Forming Logic

(Combinational)

Moore

External Output

Zs(Ys)

Excitation

Forming Logic

(Combinational)

Flip Flops

Input

Output

System Clock

Clock

External
Inputs (Xs)

Mealy

External Output

Ys Zs(Ys, Xs)

Excitation

input

Feedback

Mealy Output

Forming Logic

(Combinational)