State Diagram for a three-bit (Y 1 Y 2 Y 3 ) Full-Encoded Stoppable Counter Most standard counters such as 74XX160, 74XX161, 74XX162, 74XX163 have similar
designs.
RCO can be used to enable the next counter in the cascade (if one exists) to start counting. Below is a composite K-map for a 3-bit binary up stoppable counter with enable input EN,
asynchronous clear input CLR, and ripple-carry out RCO.
The flip-flop input excitation equation and RCO output equation can be derived from the composite K-
map or (need 3 flip-flops):D1=Y1 + = EN.Y1’.Y2.Y3 + Y1.Y2’+Y1.Y3’+EN’.Y1
D2=Y2 + = EN.Y2’.Y3 + Y2.Y3’+ EN’.Y2
D3=Y3 + = EN.Y3’ + EN’.Y3
RCO = Y1.Y2.Y3 This counter can be designed with one-hot encoding using 8 flip flops.000
001
001
010
011
100
010
011
100
101
101
110
111
000
110
111
000 001 011 010 100 101 111 110
Y 1 Y 2 Y 3
0
1
Note: CLR=1 Y 1 Y 2 Y 3 = 000(^0 0 0 0 0 0 1 0) RCO