Microsoft Word - Digital Logic Design v_4_6a

Present State
(PS/NS)
Yi Yi+

Ji Ki

Comment

User for 1s

(Set-Hold 1)

Use for 0s

(Clear-Hold 0)

0 0

0 1

1 0

1 1

0 -

1 -

- 1

- 0

Hold 0 transition

Set transition

Clear transition

Hold 1 transition

Ji

Ki

Ji’

Ki’

**Note: “-“ indicates don’t care

 The “Set – Clear Method” can be used to obtain the J-K excitation equations for the 1s of

each state variable (flip-lop outputs)

Ji = ∑ (PS .external input conditions for set) when Yi = 0 for i=1,2,3,...

Ki = ∑ (PS .external input conditions for clear) when Yi = 1 for i=1,2,3,...

Note: This method solves for 1’s of the function.

 We could also apply the “Hold 0 - Hold 1 Method” to obtain the T excitation equations for the

0s of each state variable (flip-flop outputs)

Ji’ = ∑ (PS .external input conditions for hold 0) when Yi = 0 for i=1,2,3,...

Ki’ = ∑ (PS .external input conditions for hold 1) when Yi = 1 for i=1,2,3,...

Note: This method solves for 0’s of the function and it is equivalent to first method.

 Example - J-K excitation Equation from state diagram

Design a synchronous 2-bit Binary up down counter that counts up when input signal X=0 and

counts down when input signal X=1

State  Y1Y2

Input  X

 Use the “Set – Clear Method” to obtain the J-K excitation equations for the 1s of each state

variable (flip-flop outputs)

• By observing all the sets (Y1 =0  Y1 +=1), we can write the J1 excitation equation, from
  the state diagram:
  J1 = Y1’.Y2.X’ + Y1’.Y2’.X = Y2’.X + Y2.X’


• By observing all the clears (Y1 =1  Y1+=0), we can write the K1 excitation equation,
  from the state diagram:
  K1 = Y1.Y2’.X + Y1.Y2.X’ = Y2’.X + Y2.X’

 Repeat Step 1 for the second Flip Flop

Use the “Set – Clear Method” to obtain the J-K excitation equations for the 1s of each state

variable (flip flop outputs)

• By observing all the sets (Y2 =0  Y2 +=1), we can write the J2 excitation equation, from
  the state diagram:

a

00

b

01

c

10

d

11

X’

X

X’

X

X’

X

X’

X