Microsoft Word - Digital Logic Design v_4_6a

6.2. State Minimization and FSM Design Process

The state minimization is done after the fourth step of the seven steps of Finite State Machine (FSM)
classical design:

1) Organize the Design Specifications –Using one or more of the following:

Timing Diagram, State Diagram, ASM Chart or Present State/Next State (PS/NS) table

2) Determine the number of flip-flops based on the number of states.

Full encoding  2 #flip-flop ≥ # states

or

one-hot encoding  #flip-flop = # States

Next assign one present state variable to each flip-flop output.

3) Assign a unique code to each state (a specific value for present-state variables).

4) Select the flip-flop type to be used, then determine the excitation input equations and the Moore

and/or Mealy output equations.

The excitation-input equations for common flip-flops are shown below:

JK  Y+ = J.Y’ + K’.Y

T  Y+ = T XOR Y

....D  Y+ = D

5) Draw the circuit schematic (pencil/paper or CAD tools).

6) Perform a simulation to test the functionally of the design.

7) Implement the design in hardware.

“State Minimization using

implication Chart is used

at this point”