Microsoft Word - Digital Logic Design v_4_6a

7.4. Syntax

Verilog HDL Syntax is similar to C programming Language. Below are some of the Verilog basic
language syntax:

 Identifiers
Variables, labels and module names are identifier. Verilog allows identifier to be specified by letters
or underscore followed by more letters, digits, dolor sign ($) or underscore (_) up to a maximum of
1024 character. Below are few examples of valid identifiers:
 test_213?
 count
 _count

 Note that Reserve words (Verilog commands and keywords) may not be used as identifiers:

always

and

assign

attribute

begin

buf

bufif0

bufif1

case

casex

casez

cmos

deassign

default

defparam

disable

edge

else

end

endattribute

endcase

endfunction

endmodule

endprimitive

endspecify

endtable

endtask

event

for

force

forever

fork

function

highz0

highz1

if

ifnone

initial

inout

input

integer

join

medium

module

large

macromodule

nand

negedge

nmos

nor

not

notif0

notif1

or

output

parameter

pmos

posedge

primitive

pull0

pull1

pulldown

pullup

rcmos

real

realtime

reg

release

repeat

rnmos

rpmos

rtran

rtranif0

rtranif1

scalared

signed

small

specify

specparam

strength

strong0

strong1

supply0

supply1

table

task

time

tran

tranif0

tranif1

tri

tri0

tri1

triand

trior

trireg

unsigned

vectored

wait

wand

weak0

weak1

while

wire

wor

xnor

xor

 Comment
Any information appearing after “//” on a line is considered comment:

// this is comment for the reader

Like C, Verilog considers text between “/*” and “*/” as comment and it may span multiple lines”

/* firs line of comment

could more line

then end here */

 Case Sensitivity
Verilog is case sensitive which means keywords and variable must be in correct case or it will not be
consider the same. For example Count and count are two variables. By the way all keywords in
Verilog are in lower case. In this document all keywords are in bold.