Microsoft Word - Digital Logic Design v_4_6a

7.5. Assignments

Verilog understand that there two types of element in digital design:

 Combinational – gates and other circuitry with no memory

 Sequential – flip flop and other circuitry with memory

In order to handle both types of element, Verilog identifies three types of blocks to direct the execution of
a module functionality. The three blocks are initial, assign and always which are described in detail
below:

 Initial Block “initial”

Initial statement ensures that the assignments are made only once at the beginning during the

simulation. It is typically used to initialize variables at the start of the code. Below is a usage

example:

 Assign Block “assign ”

Assign statement is used for modeling only combinational logic and it is executed continuously.

So assign statement called continuous assignment statement as there is no sensitive list.

for example in the following statement, value of variable present will be set to value in next as

long as the code is active.

assign present=next;

Note assign does one statement at a time and sequentially and it is used for combinational login

only.

module example(Ain, Bin, Cout);

input Ain, Bin;

wire Ain, Bin;

output Cout;

wire Cout;

integer i, count;

Initial // set the initial value of variables.

begin

i = 0;

count =0;

Ain =0;

Bin =0;

end //initial

endmodule // end of module