7.7. Types and Variable Declarations
Verilog requires explicit declaration of variables which means before using a variable it must be declared.
It is important to note that Verilog performs automatic type conversion. Variables in general are either of
the net data type or variable data types.
Net Data Types
“wire” is a Net data type which means it must be driven. Typically input port is of the type wire. Net
data type is used to connect components and can have strength modifiers supply0, supply1, strong0,
strong1, pull0, pull1, weak0, weak1, highz0, highz1, small, medium, large). Wire is implements
interconnection.
Example -
wire clk; // clk is declared as wire which need to be driven Variable Data
A Variable data type behaves similar to variables in c, it changes its value upon assignment and
holds its value until another assignment. The five common Variable types are:
integer Type
integer is typically a 32 bit 2’s complement integer. Example -
integer count; // declare count as an integer real
Type real is typically a 64 bit using the double precision floating point IEEE Standard format. Example -
real earnedSalary; realtime
realtime is used to storing time as a real type (floating point value). Example -
realtime now; reg type
By default reg is a one bit unsigned value and may have a sign modifier. It could use a vector
modifier [msb:lsb] to declare a multi-bit reg. We typically use reg to declare the output port type
and is typically implemented using flip flops. Example -
reg done; // declare done as a one bit value
reg [15:0] results; // declare results as a bit vector with bits 0 as least significant bit (lsb)
// and 15 as the most significant bit (msb) time type
The system function $time returns simulation time in time type. In most systems time is 64 bit
unsigned integer value.