Microsoft Word - Digital Logic Design v_4_6a

8.5. Declarations

 Signal and Variable Declarations
Signal declaration gives the same information about a signal as in a port declaration, except that
mode specification is not required. Syntax for signal declaration is shown below:

signal signal_names : signal_type;

Any number of signals can be defined within architecture, and they roughly correspond to the named

wires in a logic diagram.

It is important to note that symbol “<=” is used to assign a value to a signal. For example to assign a

value of 4 to a signal stemp, it needs to be written as follows:

stemp <= 4;

VHDL variables are similar to signals except that they do not have a physical significance in a circuit.

Variables are used within functions, procedures and processes (not used in architecture definition).

The variable declaration syntax is as follows:

variable variable_name : variable_type;

It is important to note that symbol “:= ” is used to assign a value to a variable. For example to assign

a value of 4 to a variable vtemp, it need to be written as follows:

vtemp := 4;

 “type” Declarations
All signals, variables and constants in a VHDL program must have an associated “type.” Each “type”
specifies the range of values that object can take on. “type” may be pre-defined or user defined.

 Pre-Defined Types:

 Bit

Takes on ‘0’ and ‘1’ values

 Bit-vector

array of bits

 Boolean

True, False { EQ <= True;}

 Integer

A whole number ranging from -2^31 +1 through +2^31 -1 {count <= count + 2;}

 Real

1.0, -1.0E5 {V1 := V2 / 5.3}

 Character

All of the ISO 8-bit character set – the first 128 are the ASCII Characters. {CharData <= ‘X’;}

Note: The symbol ‘ is used for character definition.

 String

An array of characters {msg<=”MEM:” & Addr;}

Note: The symbol “ is used for string definition.

 Time

1 us, 7 ns, 100 ps {Q<=’1’ after 6 ns;}