Microsoft Word - Digital Logic Design v_4_6a

Predefined Operators
VHDL is a strongly typed language which means that the complier issues error messages if types
in an operation or assignment do not perfectly match.

The integer and Boolean Operations are the most commonly used VHDL operation and operands

in each operation group must have the correct type in order for the operation to be compiled

correctly.

Following table list some of the most common operations:

Integer Operators Boolean Operators

+

• /
  mod
  rem
  abs
  **

addition

subtraction

multiplication

division

module division

module remainder

absolute value

exponentiation

and

or

nand

nor

xor

xnor

not

AND

OR

NAND

NOR

Exclusive OR

Exclusive NOR

Complementation

User-Defined Types
Although VHDL provides an extensive list of pre-defined types, user may need to define new
types using the user-defined type capabilities of VHDL. The flowing pages, describe the most
common user-defined type constructs:

 Numeration

Numeration enables the user to define a type that can only accept a predefined set of values.

The following syntax, allow definition of numeration type and its use to build two different type

of arrays:

type type_name is (value_list); -- Value-list is a comma-separated list of all

-- possible values of the type

-- create an array of type-name with an ascending order from start to end

subtype subtype_name is type_name range start to end;

-- create an array of type-name with a descending order from start to end

subtype subtype_name is type_name range start downto end;

• Example – Write a code segment to define an array that starts from 20 to -4 with each
  element value restricted to either red, green, or blue.

type COLORS is (“red”, -- User-define types are typically in Capital Letters

“green”,

“blue”,

);

subtype my_colors is COLORS range 20 downto -4;

• Example- Define a complete logic type that includes hi-z, weak and forcing.

type STD_ULOGIC is (

‘U’, -- Uninitialized

‘X’, -- Forcing Unknown

‘0’, -- Forcing 0

‘1’, -- Forcing 1

‘Z’, -- High Impedance